Early commercialmomentum 50$24B raised in 12 months22 companies
Making chips with ever smaller transistors, new transistor shapes and power wiring, and stacking many chips into one package.
Why early commercial: Intel launched Core Ultra Series 3, the first compute platform built on Intel 18A with gate-all-around transistors and backside power. Jan 5, 2026This week: The Energy Department designated helium as a critical material and the US announced R&D funding for fusion power machines.
Dots under a month: dated events tracked here that month.
Designation reflects helium’s essential role in semiconductor manufacturing and advanced energy technologies.
The U.S. Department of Commerce announced letters of intent for $389 million in research and development funding for four companies. The proposed fusion awards include $175 million for Helion Energy and $85 million for Commonwealth Fusion Systems. The funding aims to advance domestic semiconductor i
The U.S. National Science Foundation today announced an initiative to translate low-dimensional semiconductor technologies from laboratory demonstrations into platforms for U.S. manufacturers to develop and deploy advanced microelectronics. The NSF…
Samsung plans High-NA EUV for future DRAM and joins the 12-inch photomask effort.
They aim for a 12-inch mask pilot line by 2031.
Led by Trace Capital, Innovation X
Led by J.P. Morgan, Goldman Sachs
Led by Seligman Ventures
Led by Ares Management, InnoVen Capital
Led by Information-Technology Promotion Agency (IPA), Japan
Led by Information-Technology Promotion Agency (IPA), Japan
Led by Maverick Silicon
Led by Samsung Securities, AFW Partners
Does semiconductor research on nanosheet transistors and partners with Rapidus on 2nm.
Its foundry makes the Exynos 2600 on what it calls the first 2nm gate-all-around process.
Builds EUV and High-NA EUV lithography systems used for leading-edge nodes.
Runs Intel Foundry, whose 18A node combines RibbonFET gate-all-around transistors with PowerVia backside power.
Largest contract chipmaker, with N2 nanosheet, A16 backside power, and CoWoS and SoIC packaging.
Runs panel-level advanced packaging fabs for chiplet integration in Singapore and plans one in Italy.
Publishes on Advanced semiconductors at Nanjing Agricultural University: 50 papers in 2 years.
Publishes on Advanced semiconductors at Ewha Womans University: 64 papers in 2 years.
Publishes on Advanced semiconductors at First Affiliated Hospital of Xi'an Jiaotong University: 57 papers in 2 years.
Publishes on Advanced semiconductors at China Three Gorges University: 50 papers in 2 years.
Nanoelectronics R&D hub running the EU NanoIC pilot line for beyond-2nm chips.
Singapore institute researching advanced packaging and heterogeneous integration.
Dhireesha Kudithipudi, Catherine D. Schuman, Craig Michael Vineyard et al. · Nature
Suo Gao, Herbert Ho‐Ching Iu, Uğur Erkan et al. · IEEE Transactions on Circuits and Systems for Video Technology
Heyi Huang, Xiangpeng Liang, Yuyan Wang et al. · Nature Nanotechnology
Daniele Ielmini, Giacomo Pedretti · Chemical Reviews
Mario Lanza, Sebastian Matias Pazos, Fernando Leonel Aguirre et al. · Nature
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Intel Corp
Intel Corp
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Applied Materials Inc
Applied Materials Inc
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